Technology for designing and implementing integrated circuits continues to seek implementation of faster devices, while limiting the increase, or possibly even decreasing the size and power consumption of the integrated circuits. Throughout the many advances in speed and power consumption of integrated circuits, the design and implementation of such circuits has relied on “off the shelf” Boolean logic elements such as logical OR gates, NOR gates, AND gates, NAND gates, XOR gates, INVERTERS, etc.
CMOS circuits have been developed which implement the basic Boolean logic elements. These logic elements are referred to as basic elements. Logical Boolean functions are represented within integrated circuits by multi-transistor equivalent structures. When designing an integrated circuit, typically a designer will enter a program through an interface means such as a keyboard, using a known programming language. The program is translated into its equivalent basic Boolean elements by a compiler, including the connections between the outputs and inputs of various elements. Transistors comprising the integrated circuit are configured by the compiler to conform to this gating arrangement. Accordingly, Boolean logic is particularly amenable to implementation in computer systems. The process of designing and configuring an integrated circuit according to pre-determined transistor configurations is well known to those skilled in the art. FIGS. 1–4 illustrate common Boolean gates and the transistor equivalents currently used to represent these gates in a CMOS circuit.
FIG. 1 illustrates a logical NOR gate 101 as found in the prior art comprising inputs A and B, and output OutC, a truth table 103 corresponding to the logic of the NOR gate 101, and a four-transistor configuration 105 with inputs A and B and output OutC typically used in CMOS circuitry to reproduce the truth table 103 defining the input/output relationships generated the NOR gate 101.
FIG. 2 illustrates a logical NAND gate 107 as found in the prior art comprising inputs D and E, and output OutF, a truth table 109 corresponding to the logic of the NAND gate 107, and a four-transistor configuration 111 with inputs D and E and output OutF typically used in CMOS circuitry to reproduce the truth table 109 defining the input/output relationships generated by the NAND gate 107.
FIG. 3 illustrates a logical OR gate 113 as found in the prior art comprising inputs G and H, and output OutI, a truth table 115 corresponding to the logic of the OR gate, which is commonly configured from a four-transistor NOR gate 117 coupled with a two-transistor inverter 119. The output Out(NOR) of the NOR gate 117 is input into the gates of the P-channel and N-channel transistors of the inverter 119, and the state of the output OutI of the inverter behaves according to the states found in the truth table 115.
FIG. 4 illustrates a logical AND gate 121 as found in the prior art comprising inputs J and K, and output OutL, a truth table 123 corresponding to the logic of the AND gate, which is commonly configured from a four-transistor NAND gate 125 coupled with a two-transistor inverter 127. The output Out(NAND) of the NAND circuit 125 is input into the gates of the P-channel and N-channel transistors of the inverter 127, and the state of the output OutL of the inverter behaves according to the states found in the truth table 123.
Those skilled in the art will recognize that the AND and OR functions of FIGS. 3 and 4 may be equally simulated by inverting the respective outputs, as shown, or inverting both inputs (E and F) and (G and H) and inputting these inverted inputs into standard NAND and NOR gates respectively.
FIG. 5 illustrates a logical XOR (“Exclusive OR”) circuit 135 and a truth table 137 disclosing the logical relationship of the inputs and outputs of an XOR function. As noted in the XOR circuit diagram 135, the inputs to the XOR circuit include M, N, and inverted forms {overscore (M)} and {overscore (N)}. The total transistor count is therefore increased by the presence of inverter circuits 131, 133 to generate the inverted signals {overscore (M)}, {overscore (N)}.
Those skilled in the art will recognize that virtually all computer commands are reducible into discrete Boolean functions, and that Boolean algebra allows for the reduction of many complex Boolean functions into smaller and simpler Boolean expressions. Ideally, a computer programmer will reduce any complex Boolean function into the smallest and simplest representation. In conventional circuit design, these Boolean functions provide the basic elements forming sequences of logic functions. These Boolean functions are typically subdivided into one or more logical sequences which are configured on separate processing paths within an integrated circuit.
As illustrated in FIG. 6, a “logical sequence,” refers to the sequence of Boolean logic elements between an input flip flop at the beginning of a processing path and an output flip flop at the end of the processing path. Typically, an integrated circuit includes a series of such processing paths. Depending on the integrated circuit, the number of separate processing paths may run from a single processing path to millions of separate processing paths. There is no upward limit on the number of possible paths.
Within the integrated circuit, Boolean functions within each path are executed, in a quasi-serial manner according to the logical elements comprising the data path. For example, the Boolean equation (R+S)·(T+U), as illustrated in the logical circuit of FIG. 7, performs the two OR functions 160, 162 simultaneously, and then subsequently inputs the results from the OR gates 160, 162 into an AND gate 164. Although the simultaneous operation of the OR operators 160, 162 illustrates that there may be parallel operations within a logical sequence of elements, in abstract block-type diagrams of FIG. 6, the processing paths are typically illustrated as exclusively serial functions. Those skilled in the art will therefore understand that, as used herein, terms such as “serial” or “sequence of elements” and equivalent terms describing the architecture and behavior of a single processing path are intended to incorporate both the parallel and serial functionality.
Within the sequence of elements illustrated in FIG. 6, an input flip flop 138 is located at the start of a processing path, and an output flip flop 139 is located at the end of the processing path. The various elements 141–151 along the processing path represent logic elements or gating functions as illustrated in FIGS. 1–5 above, disposed in the data path between the input flip flop 138 and the output flip-flop 139. The flip-flops 138, 139 are used to hold the state of the last calculation and only transition on a clock pulse, typically the leading edge of the pulse. The logic elements 141–151, however, produce an output that reflects the “last state” of the inputs, even if an input changes state in the middle of a clock cycle. Accordingly, the logic elements within a processing path are therefore able to change state and advance logic between clock pulses. As discussed in conjunction with FIG. 7 above, this gives rise to the “quasi-serial” nature of a data path. As noted, the AND operation 164 can only take place after the two OR operations 160, 162 have been completed. If inputs into an element 164 arrive non-simultaneously, the output state of an element may change several times in a single clock pulse. Signal transmission along the processing path, however, including all intermediary state changes, must be completed before the final states are recorded in the output flip flop 139. Because the logic of a data path must be completed and the output flip flop 139 must be set within the period of a single clock pulse, it is essential that the time needed to execute a logic path between an input flip flop 138 and an output flip flop 139 is not greater than the period of a single clock pulse. The clock speed of a chip, and consequently its performance, is therefore limited by the speed at which a pulse travels from the input flip-flop 138 through the sequence of logic elements 141–151 and records the output value in the output flip-flop 139. A 200 MHz chip allows 4 nano seconds (4000 pico seconds) per logic path between clock cycles. As seen in FIG. 6, the time for a signal to completely traverse a flip-flop is represented by t1, which is typically on the order of 400 pico seconds in current designs. The time to traverse a basic logic element is represented by t2. For a four-transistor element, the time to traverse a basic logic element is typically on the order of 150 pico seconds in 130 nanometer manufacturing processes. The transmission time between elements, represented by t3, is typically on the order of 50 pico seconds in current designs. These time delays are not fixed, and will vary according to present and future design manufacturing processes and architectures. The specific time delays listed herein are therefore offered simply for exemplary purposes to illustrate more clearly the principles set forth in the present invention.
A data path operating at these conventional speeds may sustain up to sixteen logic elements between the input flip flop 138 and the output flip-flop 139 and remain within the 4 nano second clock cycle. These time delays are exemplary however, and in actual practice, current integrated circuits are typically configured with an upper limit of twenty logic elements per path. It is anticipated that new designs are going to increase above this to twenty-two elements.
CMOS architecture advantageously utilizes P-channel transistors for pull-up, and N-channel transistors for pull down functions. Accordingly, a single input inverter (“NOT”) 131, as illustrated in FIG. 5, is seen to require two transistors. A two-input NAND gate 111, as illustrated in FIG. 2 and a NOR gate 105, as illustrated in FIG. 1, each require a four transistor structure. A two-input AND gate 121 as illustrated in FIG. 4 and an OR gate 113 as illustrated in FIG. 3, require six transistors. FIG. 5 illustrates a two-input XOR gate 135 that requires twelve transistors including the inverters 131, 133. Because the application and use of these Boolean elements are fixed in integrated circuit architecture, the delays associated with these elements are also fixed. Additionally, chip size and power consumption are largely proportional to the number of transistors in a chip. Targeted objectives in CMOS circuit design typically include the achievement of higher speed, smaller size and lower power consumption. What is needed therefore is a method and apparatus for decreasing the total time for a signal to traverse a processing path in a MOS circuit. There further exists a need for a method and apparatus for reducing the size of a MOS circuit. Additionally, the need exists for a method and apparatus for reducing the power consumed by a CMOS circuit.